A digital phase lock loop can provide an output pulse signal which is synchronized to a reference signal applied to an input of the phase lock loop. The period and all other parameters of the pulse signal are set in the hardware of the digital phase lock loop and cannot be changed without a redesign. This, in turn, precludes rapid prototyping, rapid integration into new designs and easy modification of the signal parameters in the field to meet specific user needs.
A digital phase lock loop also can provide an output pulse signal with a free running period in the absence of the reference signal at the input of the phase lock loop. The frequency or period of the free running output signal is a specified design parameter. However, if the specified running period is not an integral multiple of that of the base clock signal of the digital phase lock loop, a drift error will occur in the free running output pulse signal.